1. Field of the Invention
The present invention relates to the area of semiconductor processing. In particular, the present invention relates to a method for minimizing device variation across a wafer by adjusting oxynitride layer nitrogen concentration during rapid thermal nitridation.
2. Discussion of Related Art
The dimensions of modern semiconductor devices are continually being reduced to improve integrated circuit (IC) capabilities while increasing speed and decreasing power consumption. To accommodate this continual trend towards greater miniaturization, the semiconductor processes used in the production of ICs are constantly being refined. One area of critical importance is the formation of the gate dielectrics in metal-oxide-semiconductor (MOS) transistors—in particular the gate dielectrics of PMOS transistors. Historically, silicon dioxide (SiO2) has been the material of choice for PMOS transistor gate dielectrics. However, as the thickness of an SiO2 gate dielectric is reduced, P-type dopant atoms (e.g., boron) from the overlying polysilicon gate can penetrate the gate dielectric and lodge in the channel region of the transistor. This “dopant penetration” results in an undesirable reduction in transistor threshold voltage (Vt). To address this problem, the ultrathin gate dielectrics of modern PMOS transistors are often formed from oxynitrides (SiOxNy or nitrogen-doped SiO2). The nitrogen incorporated into such layers tends to prevent dopant penetration.
A rapid thermal nitridation (RTN) process is often used to form oxynitride gate dielectrics. In an RTN process, a wafer is subjected to high temperature heating while nitrous oxide and oxygen flow across the wafer surface. FIG. 1 shows a conventional RTN process chamber 100, which is substantially similar to the Heatpulse 8108 tool from AG Associates, Inc., a subsidiary of Metron Technology, 1350 Old Bayshore Highway, Suite 210, Burlingame, Calif. 94010. RTN chamber 100 comprises a quartz isolation tube 110 that includes a gas inlet port 111 and a gas outlet port 112. RTN chamber 100 further includes a set of upper tungsten halogen lamps 120a positioned above quartz isolation tube 110, and a set of lower tungsten halogen lamps 120b positioned below quartz isolation tube 110, all of which are enclosed by a plated heating chamber 130.
To form an oxynitride layer on a wafer 190 placed in isolation tube 110, power is provided to upper tungsten halogen lamps 120a and lower tungsten halogen lamps 120b while nitrous oxide (N2O) and oxygen (O2) flow from gas inlet port 111 to gas outlet port 112. The edge of wafer 190 closest to gas inlet port 111 is designated the “leading edge” of the wafer, while the edge of wafer 190 closest to gas outlet port 112 is designated the “trailing edge.” Note that although a wafer is generally round, wafer “edges” can be defined as indicated based on a profile view of the wafer. The leading edge and trailing edge can therefore be considered substantially opposing edges of wafer 190, as they capture the entire width (i.e., diameter) of wafer 190.
The radiant heat from lamps 120a and 120b raises the temperature of wafer 190 and also heats the nitrous oxide as it flows from the leading edge to the trailing edge of wafer 190. As described by Ellis et al. in “Nitrous Oxide (N2O) Processing for Silicon Oxynitride Gate Dielectrics” (IBM J. Res. Develop., Vol. 43, No. 3, May 1999) (hereinafter “Ellis”), the nitrous oxide molecules decompose in this high temperature environment into nitrogen gas (N2) and atomic oxygen (O). This oxygen release reaction can be described by the following equation:N2O→N2+O  (1)
The highly reactive oxygen radical liberated by this mechanism can then react with another nitrous oxide molecule to form nitric oxide (NO), as described by the following equation:N2O +O→2NO  (2)
The nitric oxide then reacts with the heated surface of wafer 190 to form an oxynitride layer. Ideally, the oxynitride layer would have a constant thickness to ensure performance consistency of later-formed devices. Unfortunately, conventional RTN chambers produce oxynitride layers having thicknesses that increase in the process gas (i.e., N2O) flow direction. For example, FIG. 2a shows a processed wafer 200 that includes an example oxynitride layer 191 formed on wafer 190 using a conventional RTN process. The thickness Tn of oxynitride layer 191 increases from a minimum thickness Tn1 at the leading edge of wafer 190 to a maximum thickness Tn2 at the trailing edge of wafer 190 (not to scale). This oxynitride thickness gradient is caused by a process temperature gradient that is typically present within conventional RTN process chambers. This thermal gradient exists because the nitrous oxide is constantly being heated as it flows across the surface of the wafer. Therefore, in addition to radiant heating, the downstream portions of the wafer receive additional convective heating that leads to higher temperatures.
FIG. 2b shows an example graph of process temperature TEMP for a typical RTN process, charted against the thickness Tn of an oxynitride layer formed by such a temperature profile. Process temperature TEMP rises from a minimum temperature Temp1 at the leading edge of wafer 190 to a maximum process temperature Temp2 at the trailing edge of wafer 190. The profile of process temperature TEMP can therefore be designated as having a “positive” gradient—i.e., increasing from the leading edge of the wafer to the trailing edge. Because the nitridation process rate is directly affected by process temperature, oxynitride layer thickness Tn tracks process temperature TEMP in a linear fashion. Therefore, the oxynitride layer thickness also exhibits a positive gradient. The specific thickness gradient depends on the particular process technology in which the oxynitride layer is to be used. For example, the thickness of an oxynitride layer for a 0.25 um process can increase from 4.8 nm to 6 nm, while a similar layer for a 0.13 um process can exhibit a thickness range from 1.8 nm to 2.4 nm.
A non-uniform oxynitride layer thickness is problematic because transistors formed on such a layer will exhibit a corresponding variation in gate dielectric thickness. FIG. 3a shows a processed wafer 300 formed from processed wafer 200 shown in FIG. 2a. Processed wafer 300 includes PMOS transistors 310a, 310b, 310c, and 310d. Transistors 310a-310d comprise source regions 312a-312d, respectively, drain regions 313a-313d, respectively, gates 311a-311d, respectively, and gate dielectrics 191a-191d, respectively. Gate dielectrics 191a-191d have thicknesses Toxa-Toxd, respectively, which are formed from oxynitride layer 191 shown in FIG. 2a. Accordingly, thicknesses Toxa-Toxd track the thickness profile of oxynitride layer 191; i.e., the gate dielectric of a transistor formed towards the trailing edge of wafer 190 (e.g., transistor 310d) will be thicker than the gate dielectric of a transistor formed towards the leading edge of wafer 190 (e.g., transistor 310a).
This variation in gate dielectric thickness from transistor to transistor is undesirable because it causes the each of transistors 310a-310d to have a different threshold voltage. FIG. 3b shows a graph of gate dielectric thickness for transistors 310a-310d shown in FIG. 3a, while FIG. 3c shows a corresponding graph of threshold voltage for transistors 310a-310d. Because the threshold voltage of a PMOS transistor is directly proportional to its gate dielectric thickness, threshold voltages Vta-Vtd of transistors 310a-310d, respectively, exhibit a linear correlation with gate dielectric thicknesses Toxa-Toxd, respectively.
Thus, the non-constant thickness of an oxynitride layer produced by a conventional RTN process can have a significant effect on the performance of subsequently formed devices. For example, in a 0.25 um process where gate dielectric thickness can vary up to 25% across the wafer, threshold voltage Vtd of transistor 310d could be 25% greater than threshold voltage Vta of transistor 310a. This in turn can lead to reduced yield and/or increased production costs as process parameters are tightened to compensate for this threshold voltage variation. Accordingly, it is desirable to provide a method for producing an oxynitride layer such that transistors formed using the oxynitride layer have a consistent threshold voltage regardless of their position across the surface of the wafer on which the oxynitride layer is formed.